datasheet 9DML0441 / 9dml0451 august 27, 2018 1 ?2018 integrated device technology, inc. 2:4 3.3v pcie clock mux 9DML0441 / 9dml0451 description the 9DML0441 / 9dml0451 devices are 3.3v members of idt's full-featured pc ie family. they su pport pcie gen1-4 common clocked (cc), separate reference no spread (srns), and separate reference independent spread (sris) architectures. the parts provide a choice of asynchronous and glitch-free switching modes, and offer a choice of integrated output term inations for direct connection to 85 ? or 100 ? transmission lines. the 9dml04p1 can be factory programmed with a user-defined power-up default configuration. typical applications servers, atca, ate, storage, master/slave applications output features ? four 1?200mhz low-power hcsl (lp-hcsl) dif pairs ? 9DML0441 default z out = 100 ? ? 9dml0451 default z out = 85 ? ? 9dml04p1 factory programmable defaults ? see an-891 for easy termination to other logic levels features ? direct connection to 100 ? (xx41) or 85 ? (xx51) transmission lines saves up to 16 resistors ? 79mw typical power consumption ? spread spectrum (ss) compatible ? factory programmed p1 device allows exact optimization to customer requirements: ? control input polarity ? control input pull up/downs ? slew rate for each output ? differential output amplitude ? output impedance for each output ? oe# pins for each output ? hcsl-compatible differential inputs; can be driven by common clock source ? selectable asynchronous or g litch-free switch ing; allows the mux to be selected at power-up even if both inputs are not running, then transition to glitch-free switching mode ? space saving 4 4 mm 24-vfqfpn key specifications ? pcie gen1?4 cc compliant ? pcie gen2?3 sris compliant ? output-to-output skew < 50ps ? pcie gen4 additive phase jitter is < 0.1 ps rms ? 12khz?20mhz additive phase jitter 285fs rms typical at156.25mhz block diagram note: resistors default to internal on xx41/xx51 devices. p1 dev ices have programmable default impedances on an output-by-output bas is. a b 4 dif3 dif3# dif2 dif2# dif1 dif1# dif0 dif0# epad/gnd gndr x2 gnd vdd3.3 vddr3.3 x2 ^oe(3:0)# dif_ina# dif_ina dif_inb# dif_inb vsw_mode ^sel_a_b#
2:4 3.3v pcie clock mux 2 august 27, 2018 9DML0441 / 9dml0451 datasheet pin configuration power management table power connections gndr ^sel_a_b# ^oe3# dif3# dif3 ^oe2# 24 23 22 21 20 19 dif_ina 1 18 dif2# dif_ina# 2 17 dif2 vddr3.3 3 16 vdd3.3 vddr3.3 4 15 gnd dif_inb 5 14 dif1# dif_inb# 6 13 dif1 7 8 9 10 11 12 gndr vsw_mode ^oe0# dif0 dif0# ^oe1# 24-vfqfpn, 4 x 4 mm, 0.5mm pitch ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor 9dml04xx connect epad to gnd true o/p comp. o/p 0 running running running 1 running low low dif_in oex# pin difx vdd gnd 324 47 16 15 dif outputs description pin number input a receiver analo g input b receiver analo g
august 27, 2018 3 2:4 3.3v pcie clock mux 9DML0441 / 9dml0451 datasheet pin descriptions pin# pin name type pin description 1 dif_ina in hcsl differential true input 2 dif_ina# in hcsl differential complement input 3 vddr3.3 pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 4 vddr3.3 pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 5 dif_inb in hcsl differential true input 6 dif_inb# in hcsl differential complement input 7 gndr gnd analog ground pin for the differential input (receiver) 8vsw_mode in switch mode. this pin selects either asynchronous or glitch-free switching of the mux. use asynchronous mode if 0 or 1 of the input clocks is running. use glitch-free mode if both input clocks are running. this pin has an internal pull down resistor of ~120kohms. 0 = asynchronous mode 1 = glitch-free mode 9^oe0# in active low input for enabling dif pair 0. this pin has an internal pull-up resistor. 1 =disable outputs, 0 = enable outputs 10 dif0 out differential true clock output 11 dif0# out differential complementary clock output 12 ^oe1# in active low input for enabling dif pair 1. this pin has an internal pull-up resistor. 1 =disable outputs, 0 = enable outputs 13 dif1 out differential true clock output 14 dif1# out differential complementary clock output 15 gnd gnd ground pin. 16 vdd3.3 pwr power supply, nominal 3.3v 17 dif2 out differential true clock output 18 dif2# out differential complementary clock output 19 ^oe2# in active low input for enabling dif pair 2. this pin has an internal pull-up resistor. 1 =disable outputs, 0 = enable outputs 20 dif3 out differential true clock output 21 dif3# out differential complementary clock output 22 ^oe3# in active low input for enabling dif pair 3. this pin has an internal pull-up resistor. 1 =disable outputs, 0 = enable outputs 23 ^sel_a_b# in input to select differential input clock a or differential input clock b. this input has an internal pull-up resistor. 0 = input b selected, 1 = input a selected. 24 gndr gnd analog ground pin for the differential input (receiver) 25 epad gnd connect to ground.
2:4 3.3v pcie clock mux 4 august 27, 2018 9DML0441 / 9dml0451 datasheet test loads alternate terminations the 9dml family can easily drive lvpecl, lvds, and cml logic. see ?an-891 driving lvpecl, lv ds, and cml logic with idt's "universal" low-power hcsl outputs? for details. absolute maximum ratings stresses above the ratings listed below can cause permanent da mage to the 9DML0441 / 9dml0451. these ratings, which are standard values for idt commercially rated part s, are stress ratings only. functional o peration of the device at these or any o ther conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters terminations device zo ( ? )rs ( ? ) 9DML0441 100 none needed 9dml0451 100 7.5 9dml04p1 100 prog. 9DML0441 85 n/a 9dml0451 85 none needed 9dml04p1 85 prog. rs rs low-power hcsl differential output test load 2pf 2pf 5 inches zo (ohms) device parameter symbol conditions minimum typical maximum units notes supply voltage vddx 4.6 v 1,2 input voltage v in -0.5 v dd +0.5 v 1,3 input high voltage, smbus v ihsmb smbus clock and data pins 3.9 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2500 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 4.6v. t a = t amb , supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum units notes input common mode voltage - dif_in v com common mode input voltage 150 900 mv 1 input swing - dif_in v swing differential value 300 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential waveform 45 55 % 1 input jitter - c y cle to c y cle j dif in differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero.
august 27, 2018 5 2:4 3.3v pcie clock mux 9DML0441 / 9dml0451 datasheet electrical characteristi cs?current consumption electrical characteristics?input/supply /common parameters?normal operating conditions t a = t amb , supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum units notes operating supply current i dd vdd, all outputs active at 100mhz 24 31 ma powerdown current i ddpd vdd, all outputs disabled 2 3 ma 1 1 input clock stopped. t a = t amb , supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum units notes supply voltage vddx supply voltage for core and analog 3.135 3.3 3.465 v ambient operating temperature t amb industrial range -40 25 85 c input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -50 50 ua input frequency f ibyp 1200mhz2 pin inductance l pin 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.74 1 ms 1,2 input ss modulation frequency pcie f modinpcie allowable frequency for pcie applications (triangular modulation) 30 31.5 33 khz input ss modulation frequency non-pcie f modin allowable frequency for non-pcie applications (triangular modulation) 066khz oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 123clocks1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until outputs are > 200 mv. input current capacitance
2:4 3.3v pcie clock mux 6 august 27, 2018 9DML0441 / 9dml0451 datasheet electrical characteristics? dif low-power hcsl outputs electrical characteristics?ou tput duty cycle, jitter, sk ew and pll characteristics t a = t amb , supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum units notes slew rate dv/dt scope averaging on, default settings 1.5 2.4 4 v/ns 1, 2, 3 slew rate matching dv/dt slew rate matching 8.1 20 % 1, 4 voltage high v high 660 783 850 7 voltage low v low -150 -24 150 7 max imum voltage vmax imum 814 1150 7 minimum voltage vminimum -300 -66 7 crossing voltage (abs) vcross_abs scope averaging off 250 368 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 17 140 mv 1, 6 2 measured from differential waveform 7 these are defaults for the 41/51 devices. they are factory adjustable in the p1 device. statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. these are defaults for the 41/51 devices, alternate settings are available in the p1 device. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscillosc ope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_minimum/maximum ( vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. t a = t amb , supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum units notes duty cycle distortion t dcd measured differentially, at 100mhz 0 0.2 0.7 % 1,3 skew, input to output t pd v t = 50% 2637 3381 4273 ps 1 skew, output to output t sk3 v t = 50% 23 50 ps 1 jitter , cy cle to cy cle t jcyc-cyc additive jitter in bypass mode 1 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform. 3 duty cycle distortion is the difference in duty cycle between the output and the input clock.
august 27, 2018 7 2:4 3.3v pcie clock mux 9DML0441 / 9dml0451 datasheet electrical characteristics?fi ltered phase jitter parameters - pc ie common clocked (cc) architectures electrical characteristics?filtered pha se jitter parameters - pcie separate reference independent spr ead (sris) architectures 5 t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum industry limit units notes t jphpcieg1-cc pcie gen 1 1.5 5 ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 0.01 0.10 ps (rms) 1,2,4,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) (pll bw of 5-16mhz or 8-5mhz, cdr = 5mhz) 0.16 0.21 ps (rms) 1,2,4,5 t jphpcieg3-cc pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.07 0.10 ps (rms) 1,2,4,5 t jphpcieg4-cc pcie gen 4 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.07 0.10 ps (rms) 1,2,4,5 1 applies to all outputs. 5 driven by 9fgl0841 or equivalent. 2 based on pcie base specification rev4.0 version 1.0. see http://www.pcisig.com for latest specifications. 3 sample size of at least 100k cycles. this fi g ure extrapolates to 108ps pk-pk at 1m cycles for a ber of 1 -12 . 4 for rms values additive jitter is calculated by solving the following equation for b [ a^2+b^2=c^2 ] where "a" is rms input jitter and "c" is rms total jitter. additive phase jitter n/a t jphpcieg2-cc t amb = over the specified operating range. supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum industry limit units notes t jphpcieg2-sris pcie gen 2 (pll bw of 16mhz , cdr = 5mhz) 0.21 0.26 ps (rms) 1,2,4 t jphpcieg3-sris pcie gen 3 (pll bw of 2-4mhz or 2-5mhz, cdr = 10mhz) 0.06 0.11 ps (rms) 1,2,4 1 applies to all outputs. additive phase jitter n/a 2 based on pcie base specification rev3.1a. these filters are different than common clock filters. see http://www.pcisig.com for latest 3 sample size of at least 100k cycles. this figure extrapolates to 108ps pk-pk at 1m cycles for a ber of 1 -12 . 4 for rms values, additive jitter is calculated by solving the following equation for b [ a^2+b^2=c^2 ] where "a" is rms input jitter and "c" is rms total jitter. 5 as of pcie base specification rev4.0 v1.0, sris is not currently defined for gen1 or gen4.
2:4 3.3v pcie clock mux 8 august 27, 2018 9DML0441 / 9dml0451 datasheet electrical characteristics? unfi ltered phase ji tter parameters marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?yyww? or ?yww? is the digits of the year and week that the part was assembled. 3. ?i? denotes industrial temperature range device. 4. ?p? denotes factory programmable defaults. 5. ?**? denotes the lot sequence. 6. ?$? denotes the mark code. thermal characteristics t a = t amb , supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions minimum typical maximum industry limit units notes t jph156m 156.25mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 114 fs (rms) 1,2,3 t jph156m12k-20 156.25mhz, 12khz to 20mhz, -20db/decade rollover <12khz, -40db/decade rolloff > 20mhz 285 fs (rms) 1,2,3 1 guaranteed by design and characterization, not 100% tested in production. 2 driven by rhode & schwartz sma100. additive phase jitter, fanout mode n/a 3 for rms values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2] where "a" is rms input jitt er and "c" is rms total jitter. lot 441ai yyww lot 451ai yyww 4p1ai 000 yww**$ parameter symbol conditions pkg typical value units notes c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 1 epad soldered to board. thermal resistance nlg24
august 27, 2018 9 2:4 3.3v pcie clock mux 9DML0441 / 9dml0451 datasheet package outline drawings the package outline drawings are appended at the end of this do cument and are accessible from the link below. the package information is the most current data available. www.idt.com/document/psc/nlnlg24p1-package-outline-40-x-40-mm-body-05-mm-pitch-qfn-epad-size-245-x-245-mm ordering information ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (wil l not correlate with the datasheet revision). ?xxx? is a unique factory assigned number to identify a particular default configuration. part / order number notes shippingpackaging package temperature 9DML0441akilf trays 24-vfqfpn -40 to +85 c 9DML0441akilft tape and reel 24-vfqfpn -40 to +85 c 9dml0451akilf trays 24-vfqfpn -40 to +85 c 9dml0451akilft tape and reel 24-vfqfpn -40 to +85 c 9dml04p1axxxkilf trays 24-vfqfpn -40 to +85 c 9dml04p1axxxkilft tape and reel 24-vfqfpn -40 to +85 c 100 ? 85 ? factory configurable. contact idt for addtional information.
disclaimer integrated device technology, in c. (idt) and its affiliated companies (herei n referred to as ?idt?) reserve the righ t to modify the products and/or specificat ions described herein at any time, without notice, at idt?s sole discretion. perfor mance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is prov ided without representation or wa rranty of any kind, whether expr ess or implied, including, but not limited to, the suitab ility of idt's products for any particular purpose, an implied warranty of merchantability, or non-infri ngement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intel- lectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datashee t type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support 9DML0441 / 9dml0451 august 27, 2018 10 ?2018 integrated device technology, inc. revision history issue date description page # 8/27/2018 1. minor updates to electrical tables. 2. updated front page text. 3. updated block diagram. various 6/6/2016 1. updated leakage current spec for inputs with pull/up/down to +/-50a. 2. updated electrical tables with characterization data. 3. update front page text. 4. updated ordering information. 5. move to final. various
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